From 96d6d17a4437101940b11ecee963dacf49c39122 Mon Sep 17 00:00:00 2001
From: Pavel Kirienko <pavel.kirienko@gmail.com>
Date: Tue, 3 Apr 2018 12:49:11 +0300
Subject: [PATCH] Added another item to the design guidelines

---
 sapog_reference_hardware/README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sapog_reference_hardware/README.md b/sapog_reference_hardware/README.md
index 0700bc5..a500d07 100644
--- a/sapog_reference_hardware/README.md
+++ b/sapog_reference_hardware/README.md
@@ -22,6 +22,7 @@ the switching time must be under 50 nanoseconds.
 Sapog employs somewhat unorthodox methods of state estimation which require a high-speed inverter.
 2. The RC filters in the phase voltage feedback circuits should be designed so that their cutoff frequency
 is around 19 kHz and the output impedance does not exceed 8 kohm.
+3. Unless your maximum supply voltage exceeds 25 V (6S), do not change the DC link voltage measurement divider.
 
 ## License